Title :
A 64 b microprocessor with multimedia support
Author :
Chamas, A. ; Dalal, A. ; deDood, P. ; Ferolito, P. ; Frederick, B. ; Geva, O. ; Greenhill, D. ; Hingarh, H. ; Kaku, J. ; Kohn, L. ; Lev, L. ; Levitt, M. ; Melanson, R. ; Mitra, S. ; Sundar, R. ; Tamjidi, M. ; Wang, P. ; Wendell, D. ; Yu, R. ; Zyner, G.
Author_Institution :
Sun Microsystems Inc., Mountain View, CA, USA
Abstract :
A quad-issue microprocessor chip implements a 64 b architecture extension to a popular 32 b RISC instruction set. Additional instructions and dedicated hardware provide up to 10/spl times/ speed-up of image processing and rendering algorithms, including video compression/decompression and texture-mapped 3D triangles. The chip contains 5.2M transistors on a 17.7/spl times/17.8 mm/sup 2/ die in 0.5 /spl mu/m CMOS with 4 metal layers. The package is a 620-pin plastic BGA with 187 power and ground pins. Operating at 167 MHz, it dissipates less than 30 W from a 3.3 V supply.
Keywords :
CMOS digital integrated circuits; computer graphic equipment; computer graphics; microprocessor chips; multimedia computing; reduced instruction set computing; 0.5 micron; 167 MHz; 3.3 V; 30 W; 64 bit; CMOS chip; RISC instruction set; architecture extension; ball grid array; image processing; multimedia support; plastic BGA; quad-issue microprocessor chip; rendering algorithms; texture-mapped 3D triangles; video compression; video decompression; CMOS logic circuits; Clocks; Delay; Hardware; Image processing; Microprocessor chips; Reduced instruction set computing; Rendering (computer graphics); Sun; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535512
