Title :
A 1.2 W 66 MHz superscalar RISC microprocessor for set-tops, video games, and PDAs
Author :
Dac Pham ; Kahle, J. ; Ogden, D. ; Putrino, M. ; Tai Ngo ; Hoover, K. ; Cang Tran ; Sweet, M. ; Hung Hua ; Quan Nguyen ; Mallick, S. ; Eisen, L. ; Loper, A. ; Chitturi, R. ; Lyon, T. ; Ho, B. ; Patel, R. ; Cheesebrough, E. ; Kuttanna, B. ; Piejko, A.
Author_Institution :
Somerset Design Center, IBM Corp., Austin, TX, USA
Abstract :
This 32 b superscalar processor, having 18 mW/MHz projected power consumption at 66 MHz, is designed for desktop companions and high-end embedded multimedia applications with graphics-intensive requirements such as high-performance video games. This processor, the latest member of the PowerPC microprocessor family, can also be used in other low-power computing applications. The processor is fabricated in a 3.3 V, 0.5 m, 4-level metal CMOS resulting in 1 M transistors in a 7.07/spl times/7.07 mm/sup 2/ chip. Dual 4 kB instruction and data caches coupled to a high-performance 64 b multiplexed bus and separate execution units (float, integer, branch, and load-store) result in 2 instructions per clock cycle peak rate. Low-power design includes dynamically-powered-down execution units. Standby power is <2 mW. CPU to bus clock ratios of 2/spl times/ and 3/spl times/ allow control of system power while maintaining processor performance.
Keywords :
CMOS digital integrated circuits; computer games; microprocessor chips; multimedia computing; notebook computers; reduced instruction set computing; 0.5 micron; 1.2 to 2 W; 3.3 V; 32 bit; 4 kB; 4-level metal CMOS chip; 66 MHz; PDA; PowerPC microprocessor family; data cache; desktop companions; dynamically-powered-down execution units; embedded multimedia applications; instruction cache; low power operation; low-power computing applications; multiplexed bus; power consumption; superscalar RISC microprocessor; video games; Clocks; Delay; Frequency; Games; Logic arrays; Logic testing; Microprocessors; Personal digital assistants; Power dissipation; Reduced instruction set computing;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535513