A multi-objective algorithm for the design of high performance reconfigurable architectures with embedded decoding

The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new computer aided design methodology for rapid design of such high performance reconfigurable embedded FPGA cores. In this paper, a power aware genetic algorithm is presented for automatic generation of target specific embedded reconfigurable cores from a library of logic blocks. The paper compares four decoding techniques within the algorithm, and explores the impact they have on the optimality of the architecture.