Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs

Author

Cho, Moonju ; Aoulaiche, Marc ; Degraeve, Robin ; Kaczer, Ben ; Franco, Jacopo ; Kauerauf, Thomas ; Roussel, Philippe ; Ragnarsson, Lars Å ; Tseng, Joshua ; Hoffmann, Thomas Y. ; Groeseneken, Guido

Author_Institution

IMEC, Leuven, Belgium

fYear

2010

fDate

2-6 May 2010

Firstpage

1095

Lastpage

1098

Abstract

For the first time, positive and negative bias temperature instability (P/NBTI) mechanisms in sub-nanometer EOT devices are investigated in this study. It is shown that PBTI degradation in sub-nanometer EOT devices occurs by interface degradation, additionally to the oxide bulk trap filling which is the dominant mechanism in over 1 nm EOT devices. For NBTI, interface degradation remains as the main mechanism in sub-nano EOT devices, and additional high contribution of the high-k bulk defects can increase the degradation below 6A EOT.

Keywords

MOSFET; high-k dielectric thin films; PBTI degradation; high-k bulk defects; interface degradation; negative bias temperature instability; oxide bulk trap filling; positive bias temperature instability; size 1 nm; subnanometer EOT devices; subnanometer EOT high-K MOSFET; Degradation; Dielectric measurements; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOSFETs; Negative bias temperature instability; Niobium compounds; Stress; Titanium compounds; NBTI; PBTI; high-k dielectrics; thin EOT;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488667

Filename

5488667