DocumentCode
2696710
Title
Improvements of NBTI reliability in SiGe p-FETs
Author
Franco, J. ; Kaczer, B. ; Cho, M. ; Eneman, G. ; Groeseneken, G. ; Grasser, T.
Author_Institution
IMEC, Leuven, Belgium
fYear
2010
fDate
2-6 May 2010
Firstpage
1082
Lastpage
1085
Abstract
NBTI reliability of buried SiGe channel p-FETs is investigated as a function of Ge concentration, SiGe layer thickness and Si cap thickness. Measurements show that NBTI reliability can be dramatically improved by varying these three parameters, i.e., increasing the Ge fraction, increasing the thickness of the SiGe layer, and reducing the Si cap thickness. Consequently, it is demonstrated that SiGe devices are a promising option for improving NBTI in highly-scaled sub-1nm EOT pFETs.
Keywords
Ge-Si alloys; MOSFET; semiconductor device measurement; semiconductor device reliability; semiconductor materials; MOSFET; NBTI reliability; Si cap thickness; SiGe; SiGe layer thickness; buried SiGe channel p-FET; highly-scaled EOT pFET; Delay; Germanium silicon alloys; Niobium compounds; Semiconductor device reliability; Silicon germanium; Stress; Surface cleaning; Testing; Threshold voltage; Titanium compounds;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location
Anaheim, CA
ISSN
1541-7026
Print_ISBN
978-1-4244-5430-3
Type
conf
DOI
10.1109/IRPS.2010.5488668
Filename
5488668
Link To Document