PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

Author

Ioannou, D.P. ; Cartier, E. ; Wang, Y. ; Mittl, S.

Author_Institution

Microelectron. Div., Semicond. R&D Center, IBM, Essex Junction, VT, USA

fYear

2010

fDate

2-6 May 2010

Firstpage

1044

Lastpage

1048

Abstract

The impact of SiO₂ interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (V_T) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.

Keywords

MOSFET; hafnium compounds; high-k dielectric thin films; semiconductor device reliability; silicon compounds; Hf-based HKMG nFET; HfO₂; PBTI response measurement; SiO₂; dielectric interface-high-k-metal-polySi gate stack architecture; interfacial layer thickness variation; nMOSFET; positive bias temperature instability; threshold voltage instability reduction; voltage acceleration; Electron traps; Gate leakage; High K dielectric materials; High-K gate dielectrics; MOSFETs; Microelectronics; Research and development; Stress; Thickness measurement; Voltage; HfO2; High-k dielectrics; PBTI; PBTI recovery; interface; layer; metal gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488679

Filename

5488679