Title :
Interface-trap modeling for silicon-nanowire MOSFETs
Author :
Chen, Zuhui ; Zhou, Xing ; Zhu, Guojun ; Lin, Shihuan
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
Interface traps generated during device operation or stress is directly related to transistor electrical characteristics and reliability as well as critical to device performance. In this paper, an interface-trap model is included in the unified compact model (Xsim) in order to physically and accurately characterize the interface-trap behavior in silicon-nanowire (SiNW) MOSFETs. The interface-trap model is verified by TCAD simulation data. Very good agreement is achieved and the effect of interface traps is accurately captured in the drain-source characteristics of SiNW MOSFETs. The physical interface-trap model is readily applicable for circuit and reliability modeling with SiNW transistors as building blocks.
Keywords :
MOSFET; elemental semiconductors; integrated circuit modelling; integrated circuit reliability; interface states; nanowires; semiconductor device models; semiconductor device reliability; silicon; Si; SiNW MOSFET; TCAD simulation data; Xsim; circuit reliability modeling; drain-source characteristics; interface trap modeling; silicon nanowire MOSFET; transistor electrical characteristics; unified compact model; Character generation; Charge carrier processes; Circuit simulation; Electric variables; Electron emission; Electron traps; Energy states; MOSFETs; Reliability engineering; Stress; SiNW MOSFETs; drain-source current; generation current; interface traps; reliability; unified compact model;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-5430-3
DOI :
10.1109/IRPS.2010.5488693
