Potential of SOI for analog and mixed analog-digital low-power applications

Author

Colinge, J.P. ; Eggermont, J.P. ; Flandre, D. ; Francis, P. ; Jespers, P.G.A.

Author_Institution

Katholieke Univ., Leuven, Belgium

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

194

Lastpage

195

Abstract

SOI technology offers significant assets for low-voltage, low-power high-speed logic. The steeper subthreshold slope of SOI MOSFETs not only improves design of low-voltage logic circuits, but also offers also opportunities for low-power analog design. Identical DC gains can be achieved in SOI and bulk either with less current or smaller geometries, or both. This is illustrated by plots of total area and stand-by current versus DC open-loop gain of two identical Miller op amps, one bulk and one SOI.

Keywords

field effect analogue integrated circuits; field effect logic circuits; mixed analogue-digital integrated circuits; silicon-on-insulator; DC open-loop gain; Miller opamps; SOI MOSFETs; high-speed logic; low-power analog design; low-voltage logic circuits; mixed analog-digital circuits; Analog circuits; Analog-digital conversion; Costs; Degradation; Geometry; Hot carriers; Random access memory; Silicon; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535519

Filename

535519

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2697695