Title :
A built-in aging detection and compensation technique for improving reliability of nanoscale CMOS designs
Author :
Dadgour, Hamed F. ; Banerjee, Kaustav
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA
Abstract :
The time-dependent degradation (aging) of device characteristics caused by Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI) are one of the major threats to the reliability of nanoscale digital CMOS designs. To address this challenge, a novel built-in aging “detection” and “compensation” technique is proposed. Performance degradation is detected using a novel area- and power-efficient sensor. Then, to improve the reliability, an adaptive Time-Borrowing (TB)-based compensation technique is employed, which decreases the timing failure probabilities in spite of aged transistors. It is shown via simulations that by employing these techniques, the reliability of circuits can be improved by approximately 10X.
Keywords :
CMOS digital integrated circuits; ageing; compensation; hot carriers; integrated circuit design; integrated circuit reliability; nanoelectronics; BTI; HCI; adaptive TB-based compensation technique; adaptive time-borrowing-based compensation technique; aged transistors; area-efficient sensor; bias temperature instability; built-in aging compensation technique; built-in aging detection technique; hot-carrier injection; nanoscale digital CMOS design reliability; power-efficient sensor; time-dependent degradation; timing failure probability; Aging; Circuits; Degradation; Detectors; Flip-flops; Human computer interaction; Nanoscale devices; Sensor phenomena and characterization; Timing; Voltage; Aging; Bias-Temperature Instability; Diagnostics; Fault-Tolerance; Hot-carrier Effect; NBTI; PBTI; Process Variation; Reliability; Robustness; Timing Analysis;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-5430-3
DOI :
10.1109/IRPS.2010.5488727