A novel zero-overlap/enclosure metal interconnection technology for high density logic VLSIs

Author

Shibata, H. ; Ikeda, N. ; Nagamatsu, M. ; Asahi, Y. ; Maeguchi, K.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1990

fDate

12-13 Jun 1990

Firstpage

15

Lastpage

20

Abstract

A novel metal interconnection structure with self-defined metal overlap/enclosure of contact/via-hole technology utilizing polysilicon side-wall spacers and plug (SEMOCS) is proposed. It can realize a drastic reduction of metal pitch for high-density logic VLSIs. In addition, by applying a selective CVD-W technique to the via-hole filling, zero metal overlap of the via was also achieved. To verify the advantages of the technology, it was applied to a 32-b CMOS multiplier with triple-level metal interconnections. The chip area was reduced and higher-speed multiplication was achieved due to the reduction of parasitic capacitance resulting from the shrinkage of diffusion area and metal length

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated logic circuits; metallisation; tungsten; 32 bit; Al-TiN-Ti-Si; CMOS multiplier; SEMOCS; Si; W; chip area; contact/via-hole technology; diffusion area; high-density logic VLSIs; metal interconnection technology; metal pitch; parasitic capacitance; polysilicon plug; polysilicon side-wall spacers; selective CVD; self-defined metal overlap/enclosure; triple-level metal interconnections; via-hole filling; zero metal overlap; Dielectrics; Etching; Fabrication; Impurities; Logic; Plasma applications; Plasma temperature; Plugs; Space technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1990.127837

Filename

127837