A high performance, four metal layer interconnect system for bipolar and BiCMOS circuits

Author

Wilson, S.R. ; Freeman, J.L. ; Tracy, C.J.

Author_Institution

Motorola Semicond. Products Sector, Mesa, AZ, USA

fYear

1990

fDate

12-13 Jun 1990

Firstpage

42

Lastpage

48

Abstract

Two similar four-layer metal systems have been developed to meet the requirements of MOSAIC IV and V high-performance bipolar and BiCMOS circuits. These systems have planarized surfaces obtained using an n-layer photoresist and etchback processes with PETEOS as an interlayer dielectric (ILD). The high-aspect-ratio vias are filled with a multistep hot sputtered Al process. CVD W is also being evaluated as a via fill process. The initial design rules were based on the circuit goals, performance modeling, process and material capabilities, and reliability goals. The development of these processes and the design rule selection process are discussed. Test vehicles were built, and the processes and modeling were verified. Results from the test vehicles as well as a MOSAIC IV demonstration circuit are presented

Keywords

BIMOS integrated circuits; aluminium; bipolar integrated circuits; integrated circuit technology; metallisation; tungsten; BiCMOS circuits; CVD; MOSAIC IV demonstration circuit; MOSAIC V; PETEOS; W; bipolar circuits; design rules; etchback processes; four metal layer interconnect system; high-aspect-ratio vias; interlayer dielectric; modeling; multistep hot sputtered Al process; n-layer photoresist; planarized surfaces; reliability; test vehicles; via fill process; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Circuit testing; Delay lines; Integrated circuit interconnections; Manufacturing; Materials reliability; Process design; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1990.127841

Filename

127841