A low-temperature in-situ deposition and planarizing phosphosilicate glass process for filling high-aspect-ratio topography

Author

Pennington, Scott ; Hallock, Dale

Author_Institution

IBM Gen. Technol. Div., Essex Junction, VT, USA

fYear

1990

fDate

12-13 Jun 1990

Firstpage

71

Lastpage

75

Abstract

A low-temperature (i.e. 400°C) phosphosilicate glass (PSG) passivation process has been developed that will fill high-aspect-ratio (i.e. 3:1) topography and that can be planarized in situ without a high-temperature (i.e. 800-1100°C) reflow anneal. A tetraethylorthosilicate (TEOS)/ozone chemical vapor deposition (CVD) process, with triethylphosphine (TEP) as the dopant, deposits the PSG. CVD boron oxide (B₂O₃) reflows as it is deposited and is used as a sacrificial planarization material. In addition to the high-aspect-ratio fill and in-situ planarization, the PSG process is run as an integrated sequence on a single tool, which optimizes process time and control

Keywords

chemical vapour deposition; integrated circuit technology; passivation; phosphosilicate glasses; plasma CVD; 400 degC; B₂O₃; P2O5-SiO2; PSG; high aspect ratio topography filling; in-situ planarization; integrated sequence; low-temperature in-situ deposition; passivation; phosphosilicate glass process; plasma enhanced CVD; process control; sacrificial planarization material; tetraethylorthosilicate/O₃ CVD; triethylphosphine; Annealing; Argon; Filling; Glass; Passivation; Planarization; Plasma applications; Plasma temperature; Sputtering; Surface topography;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1990.127846

Filename

127846