Optimal cell design for enhancing reliability characteristics for sub 30 nm NAND Flash memory

One of the critical scaling barriers in sub 30 nm NAND Flash technology node is an abrupt threshold voltage drop of cell transistors by short channel effect. It increases program voltage which leads, in turn, to fatal reliability issues. A simple way to relieve the short channel effect is increasing the channel boron concentration. However it degrades endurance characteristics by deteriorating boosting efficiency on inhibit operation. In this paper, we present an optimal cell design for the improved reliability characteristics in the level of mass production for the future NAND Flash with floating gate cells.