Title :
Understanding transient latchup hazards and the impact of guard rings
Author :
Farbiz, Farzan ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
An experimental study of transient latchup is conducted. Measurements are performed on test structures fabricated in 90-nm and 130-nm CMOS technologies. The worst case testing conditions differ for static and transient latchup. Device simulation is used to understand the measurement results. P-well and N-well guard rings are evaluated under transient test conditions.
Keywords :
CMOS integrated circuits; hazards; integrated circuit measurement; integrated circuit testing; invertors; transient analysis; CMOS inverter; CMOS technology; N-well guard rings; P-well guard rings; device simulation; size 130 nm; size 90 nm; test structures; transient latchup hazards; CMOS technology; Circuit testing; Computational modeling; Electrostatic discharge; Hazards; Impedance; Performance evaluation; Power supplies; Variable structure systems; Voltage; Guard rings; Latchup;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-5430-3
DOI :
10.1109/IRPS.2010.5488787
