Offset reduction in operational amplifiers using floating gate technology and LMS algorithm

An offset reduction technique using floating gate technology and LMS algorithm is presented. Offset reduction in operational amplifiers is achieved by programming two floating gate transistors that form an important part of a single-stage folded cascode amplifier. Floating-gate transistors were programmed for a minimum offset voltage of ±25μV using 1.2μm CMOS process. Programmed operational amplifiers can be used in continuous-time operation for a long period of time without the need of reprogramming. Experimental results show that LMS algorithm can be used to program efficiently floating-gate transistor in order to reduce offset voltage in operational amplifiers.