DocumentCode
2699097
Title
Gate dielectric reliability in the sub threshold regime
Author
Nicollian, Paul E. ; Chancellor, Cathy A. ; Krishnan, Anand T.
Author_Institution
Adv. CMOS Technol.-Design Integration, Texas Instrum. Inc., Dallas, TX, USA
fYear
2010
fDate
2-6 May 2010
Firstpage
385
Lastpage
390
Abstract
The dielectric reliability of devices operating in the high bias, low gate current sub threshold state that can occur in analog and mixed signal designs is investigated using substrate hot carrier injection to accelerate breakdown. The complexities of this stress mode are elucidated and a reliability projection methodology is presented.
Keywords
hot carriers; semiconductor device breakdown; semiconductor device reliability; gate dielectric reliability; low gate current subthreshold state; mixed analog signal designs; reliability projection methodology; stress mode complexity; substrate hot carrier injection; time-dependent dielectric breakdown; Acceleration; CMOS technology; Costs; Dielectric breakdown; Dielectric devices; Dielectric substrates; Electric breakdown; Electron traps; MOSFETs; Stress; Breakdown; Dielectric; Hydrogen; Oxide; Reliability; SiON; Sub-threshold; TDDB;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location
Anaheim, CA
ISSN
1541-7026
Print_ISBN
978-1-4244-5430-3
Type
conf
DOI
10.1109/IRPS.2010.5488798
Filename
5488798
Link To Document