Reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology

Author

Prasad, C. ; Bai, P. ; Gannavaram, S. ; Hafez, W. ; Hicks, J. ; Jan, C.-H. ; Lin, J. ; Jones, M. ; Komeyli, K. ; Kotlyar, R. ; Mistry, K. ; Post, I. ; Tsai, C.

Author_Institution

Logic Technol. Dev. Quality&Reliability, Intel Corp., Hillsboro, OR, USA

fYear

2010

fDate

2-6 May 2010

Firstpage

293

Lastpage

298

Abstract

In this paper, we present extensive reliability characterization results for a novel dual gate 45 nm HK+MG technology. BTI, HCI and TDDB degradation modes on the Logic and I/O transistors are studied and excellent reliability is demonstrated. Emphasis is placed on the importance of process optimizations to support robust I/O transistors while maintaining the high performance and reliability of Logic transistors. Monitoring of reliability for HVM and collateral reliability are also addressed.

Keywords

electric breakdown; high-k dielectric thin films; integrated circuit reliability; logic circuits; system-on-chip; transistors; BTI; DG HK+MG technology; HCI degradation; HVM reliability; I/O transistors; SoC; TDDB degradation; dual gate oxide high-k/metal gate technology; logic transistors reliability; low power system-on-chip; process optimization; size 45 nm; time dependent dielectric breakdown; CMOS technology; Degradation; High K dielectric materials; High-K gate dielectrics; Logic; MOS devices; Niobium compounds; Power system reliability; Robustness; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488815

Filename

5488815