Gate oxide effect on wafer level reliability of next generation dram transistors

Wafer level reliability (WLR) issues of DRAM cell and peripheral transistors are discussed. Since the 70 nm technology node, recessed transistors have been accepted for assuring data retention time of DRAM cell transistors. Various recessed transistor structures suggest that the most important issue in reliability, in addition to optimizing data retention time, is the elimination of local regions of concentrated electric fields. In this paper, by modulating the cell gate oxidation process, local field concentration is effectively reduced. Particularly, the introduction of a radical oxidation process can create cell transistors that are more immune to Fowler-Nordheim (F-N) stress, which can degrade interface quality during cell transistor operation. On the other had, for DRAM peripheral transistors, for DRAM peripheral transistors, which currently use dual poly-Si gates and SiON dielectrics, high-k/metal gate (HK/MG) structure are expected to be adopted at the 20 nm technology node for improved equivalent oxide thickness (EOT) scaling. The high thermal budget of a conventional DRAM manufacturing process can significantly impact HK/MG WLR issues. However, we have evaluated reliability characteristics for HK/MG WLR on DRAM cell and peripheral devices, and concluded that WLR issues will not be critical for operation.