Effect of multiple-transistor charge collection on SET pulse widths

Author

Ahlbin, J.R. ; Gadlage, M.J. ; Atkinson, N.M. ; Bhuva, B.L. ; Witulski, A.F. ; Holman, W.T. ; Massengill, L.W. ; Eaton, P.H. ; Narasimham, B.

Author_Institution

Dept. of Elec. Eng. & Comp. Sci., Vanderbilt Univ., Nashville, TN, USA

fYear

2010

fDate

2-6 May 2010

Firstpage

198

Lastpage

202

Abstract

New heavy-ion data from a 130 nm bulk CMOS process shows a counterproductive result in using a common single-event charge collection mitigation technique. Guard bands can reduce single-event pulse widths for normal strikes, but increase them for angled strikes. Calibrated 3D TCAD mixed-mode modeling has identified a multiple-transistor charge collection mechanism that explains the experimental data, namely that angled strikes result in charge collection in the normally ON device that increases the restoring current on the struck device.

Keywords

CMOS integrated circuits; MOSFET; radiation hardening (electronics); CMOS process; SET pulse widths; calibrated 3D TCAD mixed-mode modeling; guard bands; multiple-transistor charge collection effect; single-event charge collection mitigation technique; size 130 nm; struck device; CMOS process; CMOS technology; Error analysis; MOSFETs; Microelectronics; Pulse circuits; Pulse width modulation inverters; Space vector pulse width modulation; Transistors; Voltage; SER; SET; charge sharing; pulse width; radiation environment; single event; single event transient; soft error;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488828

Filename

5488828