On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies

Author

Seifert, N. ; Ambrose, V. ; Gill, B. ; Shi, Q. ; Allmon, R. ; Recchia, C. ; Mukherjee, S. ; Nassif, N. ; Krause, J. ; Pickholtz, J. ; Balasubramanian, A.

Author_Institution

Technol. Manuf. Group, Intel Corp., Hillsboro, OR, USA

fYear

2010

fDate

2-6 May 2010

Firstpage

188

Lastpage

197

Abstract

Test chips built in a 32 nm bulk CMOS technology consisting of hardened and non-hardened sequential elements have been exposed to neutrons, protons, alpha-particles and heavy ions. The radiation robustness of two types of circuit-level soft error mitigation techniques has been tested: 1) SEUT (Single Event Upset Tolerant), an interlocked, redundant state technique, and 2) a novel hardening technique referred to as RCC (Reinforcing Charge Collection). This work summarizes the measured soft error rate benefits and design tradeoffs involved in the implemented hardening techniques.

Keywords

CMOS integrated circuits; radiation hardening (electronics); SEUT; advanced bulk CMOS technologies; alpha-particles; circuit-level soft error mitigation techniques; hardened sequential elements; heavy ions; neutrons; nonhardened sequential elements; protons; radiation hardening techniques; radiation-induced soft error performance; redundant state technique; reinforcing charge collection; single event upset tolerant; size 32 nm; Alpha particles; CMOS technology; Circuit testing; Logic devices; Neutrons; Protection; Protons; Radiation hardening; Random access memory; Single event upset; Alpha particle; Neutron; SE; SEE; hardened; heavy ion; mitigation; neutron; proton; single event effects; soft errors; space; terrestrial;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488831

Filename

5488831