Title :
A 1.9 Gbit/s monolithic comparator implemented on an analog bipolar array
Author :
Cepl, F. ; Sauerer, J. ; Hagelauer, R. ; Seitzer, D.
Author_Institution :
Fraunhofer-Gesellschaft Inst. for Integrated Circuits, Erlangen, Germany
Abstract :
A monolithic comparator with sample rates up to 1.9 Gbit/s integrated on an analog array is presented. The circuit has been implemented on an analog array in a standard bipolar process. A parallel circuit structure doubles the maximum sampling rate. The analog array has been customized with two metal layers. Performance data such as the maximum data rate of 1.9 Gbit/s demonstrate the applicability of the comparator logic test systems and high-speed data transmission circuits
Keywords :
application specific integrated circuits; bipolar integrated circuits; comparators (circuits); linear integrated circuits; 1.9 Gbit/s; analog bipolar array; comparator logic test systems; customized circuit; high-speed data transmission circuits; maximum sampling rate; monolithic comparator; parallel circuit structure; Bit rate; Circuit simulation; Clocks; Differential amplifiers; Feedback loop; Latches; Multiplexing; Sampling methods; Virtual manufacturing; Voltage;
Conference_Titel :
Bipolar Circuits and Technology Meeting, 1990., Proceedings of the 1990
Conference_Location :
Minneapolis, MN
DOI :
10.1109/BIPOL.1990.171123
