• DocumentCode
    2700232
  • Title

    Variable size analysis and validation of computation quality

  • Author

    Yamashita, Hajime ; Yasnura, H. ; Eko, Fajar N. ; Yun, Cao

  • Author_Institution
    Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    95
  • Lastpage
    100
  • Abstract
    Variable size analysis is a technique to analyze the maximum bit length of each variable in a program or an HDL description. In design of an embedded system, the size (bit length) of each variable strongly affects the size of hardware (the width of datapath and the size of memory) and power consumption of the system. In this paper, we discuss practical methods of variable size analysis in combination of the static approach and simulation based dynamic approach. The variable size analysis is also applicable to design of multimedia embedded systems. Quality of computation of the system is determined by the trade-off between quality of output and cost of systems. We also proposed a new design called quality driven design methodology based on the variable size analysis
  • Keywords
    embedded systems; high level synthesis; HDL description; computation quality; datapath; multimedia embedded systems; simulation based dynamic approach; variable size analysis; variable size validation; Computational modeling; Computer science; Costs; Data analysis; Design methodology; Embedded system; Energy consumption; Hardware design languages; Information science; System performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2000. Proceedings. IEEE International
  • Conference_Location
    Berkeley, CA
  • Print_ISBN
    0-7695-0786-7
  • Type

    conf

  • DOI
    10.1109/HLDVT.2000.889566
  • Filename
    889566