Transformation of algorithmic simulation vector sets considering mapping problems of I/O operations

In the high-level synthesis (HLS) domain, more and more often the simulation vectors are specified at algorithmic level focussing on functional behavior. Due to the HLS and the inherent changes of the cycle-by-cycle behavior, simulation vector sets (SVS) specifying synchronous behavior cannot be reused on register transfer level (RTL). An automatic transformation of the algorithmic SVS is necessary to avoid a manual and time-consuming transformation phase. One critical part of the transformation process is to determine the mapping of the I/O operations of the algorithmic specification and of the I/O operations of the algorithmic SVS. Therefore, this paper presents three alternatives to solve this mapping problem, and describes their advantages, as well as their disadvantages