An extensive study for the impacts of structure-wise TSVs on position-oriented MOSFETs with TSV signal disturbance

A comprehensive investigation for the structural and electrical influences of via-last through silicon via (TSV) process on the 0.18-μm MOSFETs has been proposed in this work. The well-isolated TSVs don´t affect the threshold voltages and drain currents in terms of the MOSFET distances to the TSVs, the size of the TSVs, the configuration of TSVs, and the positions of MOSFETs by the TSVs. Over-wafer characteristics profile wouldn´t spread out more by TSV process. Moreover, the well configurations in the Si substrate for the MOSFETs surely relate to the interference of high-frequency signals in the TSV on the relative MOSFETs.