Scalability with silicon nitride encapsulation layer for Ti/HfOx pillar RRAM

Author

Gu, Pei-Yi ; Chen, Yu-Sheng ; Lee, Heng-Yuan ; Chen, Pang-Shiu ; Liu, Wen-Hsing ; Chen, Wei-Su ; Hsu, Yen-Ya ; Chen, Frederick ; Tsai, Ming-Jinn

Author_Institution

Electron. & Optoelectron. Res. Lab., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2010

fDate

26-28 April 2010

Firstpage

146

Lastpage

147

Abstract

In this work, the nanoscale Ti/HfO₂ based resistive memory with pillar structure was fabricated. The architecture of the pillar device shows the advantages of reduced parasitic capacitance effect and simple process flow. The effects of the passivated layer on the nanoscale RRAM are also studied. Reduction of the interaction between the memory device and the encapsulating layer plays an important role for the enlarging resistive switching window of the nanoscale RRAM. Finally, a nanoscale Ti/HfO₂ resistive memory with improved memory performance through an appropriate passivation layer was demonstrated.

Keywords

encapsulation; hafnium compounds; integrated circuit reliability; random-access storage; silicon compounds; titanium; SiN; Ti-HfO₂; Ti-HfOx pillar RRAM; nanoscale RRAM; nanoscale Ti-HfO₂ based resistive memory; passivated layer effect; reduced parasitic capacitance effect; resistive switching window; silicon nitride encapsulation layer; Atomic layer deposition; Degradation; Encapsulation; Hafnium oxide; Nanoscale devices; Parasitic capacitance; Scalability; Silicon; Temperature; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-5063-3

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2010.5488909

Filename

5488909