DocumentCode
2700716
Title
Bit Cost Scalable (BiCS) flash technology for future ultra high density storage devices
Author
Nitayama, Akihiro ; Aochi, Hideaki
Author_Institution
Device Process Dev. Center, Toshiba Corp., Yokohama, Japan
fYear
2010
fDate
26-28 April 2010
Firstpage
130
Lastpage
131
Abstract
We´ve developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We´ve advanced it to Pipe-shaped BiCS flash memory with U-shaped NAND string, improving the operation window and the reliability and realizing the Multi-Level-Cell (MLC) operation. The functionality has been successfully demonstrated using the 32 Gbit test chip with the 16 stacked layers and the MLC operation by 60nm P-BiCS flash technology.
Keywords
flash memories; bit cost scalable flash technology; three-dimensional memory; ultra high density storage devices; Conductivity; Costs; Delay estimation; FETs; Flash memory; Leakage current; Plugs; Stacking; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
978-1-4244-5063-3
Electronic_ISBN
1524-766X
Type
conf
DOI
10.1109/VTSA.2010.5488917
Filename
5488917
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