Title :
Bit Cost Scalable (BiCS) flash technology for future ultra high density storage devices
Author :
Nitayama, Akihiro ; Aochi, Hideaki
Author_Institution :
Device Process Dev. Center, Toshiba Corp., Yokohama, Japan
Abstract :
We´ve developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We´ve advanced it to Pipe-shaped BiCS flash memory with U-shaped NAND string, improving the operation window and the reliability and realizing the Multi-Level-Cell (MLC) operation. The functionality has been successfully demonstrated using the 32 Gbit test chip with the 16 stacked layers and the MLC operation by 60nm P-BiCS flash technology.
Keywords :
flash memories; bit cost scalable flash technology; three-dimensional memory; ultra high density storage devices; Conductivity; Costs; Delay estimation; FETs; Flash memory; Leakage current; Plugs; Stacking; Testing; Very large scale integration;
Conference_Titel :
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-5063-3
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2010.5488917
