A fast bipolar SRAM with a novel cell concept

A novel 6T memory cell based on differently operating merged transistor types is presented. An UP/DOWN memory cell concept is used. As an appropriate vehicle, a bipolar 1 K-SRAM with 1.5 μm minimum emitter stripe width was fabricated. It was demonstrated that the applied design method allows a technology-based circuit optimization and a prediction of the achievable improvement by structure refinements. Mixed-level simulation with numerical device models makes it possible to analyze the relation between technological parameters and circuit behavior, and hence is an efficient iterative procedure for obtaining optimized speed results, thus saving a number of cost- and time-intensive technology test runs