Title :
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
Author :
Khakifirooz, A. ; Cheng, K. ; Kulkarni, P. ; Cai, J. ; Ponoth, S. ; Kuss, J. ; Haran, B.S. ; Kimball, A. ; Edge, L.F. ; Reznicek, A. ; Adam, T. ; He, H. ; Loubet, N. ; Mehta, S. ; Kanakasabapathy, S. ; Schmitz, S. ; Holmes, S. ; Jagannathan, B. ; Majumdar
Author_Institution :
Albany Nanotech, IBM Res., Albany, NY, USA
Abstract :
The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity requirement.
Keywords :
CMOS integrated circuits; integrated circuit design; silicon-on-insulator; system-on-chip; device variability; extremely thin SOI CMOS technology; general purpose system-on-chip; low power system-on-chip; parasitic capacitance; silicon thickness; wafer uniformity; CMOS technology; Costs; Epitaxial growth; Fluctuations; Immune system; Logic devices; MOSFET circuits; Parasitic capacitance; Silicon; System-on-a-chip;
Conference_Titel :
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-5063-3
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2010.5488928
