Verifying thermal/thermo-mechanical behavior of a 3D stack — challenges and solutions

Author

Marchal, Paul ; Van der Plas, Geert ; Limaye, Paresh ; Mercha, Abdelkarim ; Thijs, Steven ; Linten, Dimitri ; Guruprasad, Katti ; Stucchi, Michele ; Vandevelde, Bart ; Bronckers, Stephane ; Minas, Nikolas ; Cupac, Miro ; Dehan, Morin ; Nelis, Marc ; Agarw

Author_Institution

IMEC, Leuven, Belgium

fYear

2010

fDate

26-28 April 2010

Firstpage

104

Lastpage

105

Abstract

The paper describes the design challenges for a low-cost 3D Cu-TSV technology. Based on experimental characterization, we´ll indicate the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow hereto which leverages information captured by “smart mechanical samples” .

Keywords

chip scale packaging; thermal management (packaging); three-dimensional integrated circuits; 3D stack; chip package codesign flow; chip stack; low-cost 3D Cu-TSV technology; thermo-mechanical behavior; thermo-mechanical simulation; Costs; Packaging; Power dissipation; Random access memory; Temperature measurement; Temperature sensors; Thermal management; Thermal stresses; Thermomechanical processes; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-5063-3

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2010.5488929

Filename

5488929