A 1.9 ns/6.3 W/256 Kb bipolar SRAM design

The authors describe the circuit design techniques used to demonstrate the feasibility of achieving a high-speed bipolar split-emitter MTL SRAM with 256 Kb density using ECL (emitter coupled logic) peripheral circuits. A simulated access time of 1.9 ns is achieved at 6.3 W total chip power dissipation, which is below the packaging limit for the intended applications. The minimum simulated cycle time is 3 ns. These results are based on an 0.8-μm, 26-GHz f_T, double-polysilicon self-aligned bipolar technology with calibrated NPN device models. To achieve this speed and power performance at 256 Kb density, several innovative circuit techniques are used, including an array architecture, an over-writing ECL logic circuit, an address decoder circuit with active pulldown, and bit-line discharge and restore schemes