DocumentCode :
2701190
Title :
A sub-0.5 /spl mu/A/MB data-retention DRAM
Author :
Yamauchi, H. ; Iwata, Takayoshi ; Fukushima, T. ; Uno, A. ; Sawada, K. ; Fukumoto, M. ; Fujita, T.
Author_Institution :
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fYear :
1995
fDate :
15-17 Feb. 1995
Firstpage :
244
Lastpage :
245
Abstract :
This sub-0.5 /spl mu/A/MB data retention DRAM with relaxed junction biased (RTB), plate-floating leakage monitoring (PFM) and VBB biased pull down word line driver (PDPWD) extends retention time (T/sub RT/) about 3-times and reduces refresh current (I/sub RF/) to /spl les/0.4 /spl mu/A/MB. In addition, a gate-received VBB detector (GRD) and dynamically-controlled reference generators (DCRG) reduce dc retention current (I/sub DC/) to /spl les/0.1 /spl mu/A/MB. This DRAM allows a 20 MB RAM disk to retain data for 2.5 years with a single button-shaped 190 mAh lithium battery and can be substituted for SRAM.
Keywords :
DRAM chips; 2.5 year; 20 MB; DC retention current; RAM disk; VBB biased pull down word line driver; data-retention DRAM; dynamically-controlled reference generators; gate-received VBB detector; lithium battery; plate-floating leakage monitoring; refresh current; relaxed junction bias; retention time; Current measurement; Degradation; Fluctuations; Monitoring; Random access memory; Read-write memory; Semiconductor device measurement; Solid state circuits; Timing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
ISSN :
0193-6530
Print_ISBN :
0-7803-2495-1
Type :
conf
DOI :
10.1109/ISSCC.1995.535540
Filename :
535540
Link To Document :
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