Title :
A 29 ns 64 Mb DRAM with hierarchical array architecture
Author :
Nakamura, M. ; Takahashi, T. ; Akiba, T. ; Kitsukawa, G. ; Morino, M. ; Sekiguchi, T. ; Asano, I. ; Komatsuzaki, K. ; Tadaki, Y. ; Songsu, C. ; Kajigaya, K. ; Tachibana, T. ; Satoh, K.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
This paper describes the experimental results of a 64 Mb DRAM test chip fabricated in 0.25 /spl mu/m CMOS using a segment driver circuit in a hierarchical word line scheme for shrinkability to the next-generation high-speed high-density DRAM. This approach is applicable to the prior generation.
Keywords :
CMOS memory circuits; DRAM chips; memory architecture; 0.25 micron; 29 ns; 64 Mbit; CMOS technology; hierarchical array architecture; high-speed high-density DRAM chip; segment driver circuit; word line scheme; CMOS memory circuits; Circuit testing; Delay effects; Driver circuits; MOS devices; Random access memory; Switches; Timing; Voltage; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535541
