Title :
A 150 MHz 8-banks 256 Mb synchronous DRAM with wave pipelining methods
Author :
Hoi-Jun Yoo ; Kee-Woo Park ; Chang-Ho Chung ; Seung-Jun Lee ; Hak-Jun Oh ; Jin-Seung Son ; Ki-Hong Park ; Ki-Won Kwon ; Jeong-Dong Han ; Wi-Sik Min ; Kye-Hwan Oh
Author_Institution :
Hyundai Electron. Inc., Ichon, South Korea
Abstract :
A 256 Mb synchronous DRAM with 8 banks of 32 Mb arrays introduces (1) post charge logic in the critical timing paths, (2) a wave pipelining in the data path and (3) hierarchical I/O architecture. This simplifies the latency control and leads to a fully-synchronous operation to the external clock at 150 MHz.
Keywords :
DRAM chips; pipeline processing; 150 MHz; 256 Mbit; arrays; critical timing paths; data paths; eight-bank synchronous DRAM; hierarchical I/O architecture; latency control; post charge logic; wave pipelining; CMOS logic circuits; Clocks; Content addressable storage; Delay; Logic arrays; Pipeline processing; Pulse inverters; Registers; SDRAM; Switches;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535543
