A sine/cosine direct digital frequency synthesizer using an angle rotation algorithm

A quadrature direct digital frequency synthesizer (DDFS) produces 16 b sine and cosine outputs with a spurious-free dynamic range greater than 100 dBc and a tuning resolution of 0.0015 Hz at a sample rate of 100 MHz. The prototype IC contains 58,000 transistors in a core area of12 mm/sup 2/ in 1.0 /spl mu/m CMOS and dissipates 1.4 W at 100 MHz. Instead of table lookup, an angle-rotation algorithm implemented as a multiplierless feedforward datapath is used that allows easy pipelining and limits the accumulation of roundoff errors. The modular architecture permits outputs of arbitrary precision by cascading enough angle rotation stages in the datapath. The IC has a 36 b frequency control word giving a tuning resolution of 0.0015 Hz at 100 MHz. To achieve the 100 MHz clock rate in 1.0 /spl mu/m CMOS, the phase accumulator is partitioned into 22 b and 14 b carry-select adder sections. The accumulator output is truncated to 22 b providing greater than 100 dB SFDR.