Gate stack etch induced reliability issues in nitrided-based trapping storage cells

Gate stack etch profile-induced reliability issues are reviewed and discussed. A taper nitride profile, which blocks source/drain (S/D) implantation, induces an unwanted n- region. In other words, residual charges above the junctions can deplete the n- much easily and cut off the channel formation. This will cause poor string resistance distribution, worse endurance behavior, program and erase (P/E) speed degradation, and sub-threshold swing (SS) degradation in nitride trap NAND flash memories. Improvements are achieved once gate stacks are etched more vertical. In addition, the behavior of program disturbance is also affected. Depleted S/D junctions result in high potential difference between channel and junctions at disturbed cells. Such high lateral field will induce junction breakdown and excess electrons will be accelerated and injected into the nitride layer.