Title :
Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing
Author :
Khan, Muhammad Usman Karim ; Shafique, Muhammad ; Henkel, Jörg
Author_Institution :
Dept. for Embedded Syst. (CES), Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
Abstract :
The High Efficiency Video Coding (HEVC) standard aims at providing ~50% better compression compared to its predecessor (H.264) at the cost of high computational complexity. To enable HEVC video encoding in real-time scenarios, special coding support for parallelization is provided in HEVC that can be exploited by many-core systems. In this work, we present a HEVC software architecture where a video frame is adaptively divided into independent video frame regions (i.e. so-called video tiles) which are processed concurrently on multiple cores. By balancing the workload of each video tile mapped to a particular core, the total power consumption of a system is reduced (through dynamically scaling the operating frequency) under a given frame-rate constraint. We also exploit user tolerance to further curtail the HEVC workload with insignificant video quality degradation. Experimental results illustrate that the proposed approach results in ~43% power savings on a many-core system.
Keywords :
data compression; software architecture; video codecs; video coding; H.264 standard; HEVC software architecture; HEVC standard; frame-rate constraint; high computational complexity; high efficiency video coding standard; independent video frame regions; many-core systems; power consumption; power-efficient workload balancing; video quality degradation; video tiles; Complexity theory; Encoding; Hardware; Power demand; Quality assessment; Tiles; Video recording;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
DOI :
10.7873/DATE.2014.232