Reliability studies on micro-joints for 3D-stacked chip

Three-dimensional chip stacking technology is expected to be a powerful method for achieving a short wiring distance between chips, and high-density integration of the functions in the chip, and to achieve the next generation´s high-performance large-scale integration (LSI). Each vertically stacked chip is connected by a metal line that penetrates in Si that is called a TSV (Through Silicon Via). In the present study, the test element group (TEG) in the double-layered structure where a TSV was formed was made for trial purposes to develop elemental technology related to the correlation, design conditions, characteristics, and reliability that connected it to the stacking process conditions, and the thermal cycle test was executed. The junction disconnected by the thermal cycle test was observed, and the cause of the disconnection was presumed.