Title :
A CMOS/SOS process for high reliability, radiation hard, high speed memory and logic IC´s
Author :
Heuner, Robert C. ; Hwang, Mike S. ; Bismarck, Otto
Author_Institution :
Harris Corp., Somerville, NJ, USA
Abstract :
A brief description is given of a low power, high speed, radiation hardened CMOS/SOS 64-K word by 1-b static RAM designed and fabricated with 2.0 μm polysilicon and double level metal technology. The main RAM circuit design consists of an address transition detector, a bit-line prechange circuit, a multi-state row decoder, and a highly sensitive double-stage sense amplifier. The bit-line and bit-line-bar signals are normally precharged to (Vdd-Vthn) or approximately 3.5 V. The differential signals from the bit line pair are connected to the first-stage sense amplifier which feeds the output to the second-stage sense amplifier. The second-stage sense amplifier provides the current needed to drive the long, main data-line connected directly to the output buffer. The high sensing gain of the current mirror sense amplifier, which senses less than 150 mV, enables the device to achieve 35-ns fast access time
Keywords :
CMOS integrated circuits; integrated circuit technology; integrated logic circuits; integrated memory circuits; radiation hardening (electronics); random-access storage; semiconductor-insulator boundaries; 2 micron; 35 ns; 64 kbit; RAM circuit design; Si on sapphire; Si-Al2O3; access time; address transition detector; bit-line prechange circuit; bit-line-bar signals; differential signals; double level metal technology; double-stage sense amplifier; high speed CMOS/SOS; logic IC; memory IC; multi-state row decoder; radiation hardened CMOS/SOS; static RAM; CMOS integrated circuits; CMOS logic circuits; CMOS process; Cosmic rays; Delta modulation; High speed integrated circuits; Integrated circuit packaging; Notice of Violation; Redundancy; Tin;
Conference_Titel :
SOS/SOI Technology Conference, 1989., 1989 IEEE
Conference_Location :
Stateline, NV
DOI :
10.1109/SOI.1989.69821
