High performance all digital phase locked loop mathematics modeling and design

The paper introduces a novel architecture of all digital phase locked loop(ADPLL). It proposes a novel frequency acquisition method by separating frequency detecting process from phase detecting process which shortens the acquisition-time greatly. Furthermore, 1-bit quantified theory is used in ADPLL to increase the controllability of the loop. A precise mathematical model of the ADPLL is built with Matlab. Through the simulation result, the feasibility of this system is justified. Stabilization is an important performance of PLL. The proposed ADPLL is a nonlinear system, so the conventional linear system analysis theory is not suit anymore. This paper uses Lyapunov theory to test stabilization of the proposed ADPLL system.