Concept for electronic calibration of A CMOS voltage reference

In this paper an approach for a CMOS voltage reference with the ability to calibrate both voltage over temperature behavior and absolute voltage value is presented. This is achieved by electronic controlled trimming of resistances in the PTAT current source and output amplifier. For the transistors in the PTAT current source, the diode connected reference source and the error amplifier a common size of width W = 1μm and length L = 4μm was chosen. The design has a nominal total current consumption of 3.4μA and operates at a minimum supply voltage as low as 800mV for the chosen V_ref2 of 700mV. The design can be optimized for even lower current consumption by using higher resistances as well as narrower and/or longer transistors. However, such an adaption increases the chip area due to the larger size of both resistors and FETs.