Title :
Performance comparison of asynchronous adders
Author :
Franklin, Mark A. ; Pan, Tienyo
Author_Institution :
Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
Abstract :
In asynchronous systems, average function delays principally govern overall throughput. This paper compares the performance of six adder designs with respect to their average delays. Our results show that asynchronous adders (32 or 64-bits) with a hybrid structure (e.g., carry-select adders) run 20-40% faster than simple ripple-carry adders. Hybrid adders also outperform high-cost, strictly synchronous conditional-sum adders
Keywords :
adders; adders; asynchronous adders; delays; function delays; performance; throughput; Added delay; Adders; Clocks; Delay systems; Digital systems; Propagation delay; Prototypes; Reduced instruction set computing; Statistics; Throughput;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-8186-6210-7
DOI :
10.1109/ASYNC.1994.656299
