Title :
An asynchronous pipelined lattice structure filter
Author :
Cummings, U.V. ; Lines, A.M. ; Martin, A.J.
Author_Institution :
Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
Abstract :
We derive an asynchronous, delay-insensitive CMOS circuit to implement a finite impulse response lattice structure filter. Simulation indicates a performance in the range of 380 million multiplications and 980 million additions per second in Hewlett-Packard´s 0.8 μm technology (λ=0.5 μm). We obtain high throughput by using deep pipelines and buffering the carry chains of adders and multipliers. Our work demonstrates that formal design can easily yield circuits which are safe and fast
Keywords :
adders; CMOS circuit; adders; asynchronous; buffering; carry chains; deep pipelines; delay-insensitive CMOS; finite impulse response lattice structure filter; lattice structure filter; multipliers; Adders; CMOS technology; Circuits; Computer science; Delay; Design methodology; Filter bank; Finite impulse response filter; IIR filters; Lattices;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-8186-6210-7
DOI :
10.1109/ASYNC.1994.656301
