Title :
Building fast bundled data circuits with a specialized standard cell library
Author_Institution :
Dept. of Inf., Oslo Univ.
Abstract :
A method for building fast, optimized bundled data circuits from a specialized CMOS standard cell library is presented. The method has been successfully used for the design of a FIFO buffer for a multicomputer network. This chip, which contains about 19000 transistors in a 1.5 μm CMOS process, achieves a throughput of about 150 million symbols per second
Keywords :
asynchronous circuits; CMOS standard cell library; FIFO buffer; data circuits; fast bundled; multicomputer network; standard cell library; Asynchronous circuits; Circuit simulation; Delay; Informatics; Libraries; Logic circuits; Pipeline processing; Safety; Throughput; Timing;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-8186-6210-7
DOI :
10.1109/ASYNC.1994.656302
