CSP present and future

Author

Magill, Paul A. ; Baggs, Joseph W.

Author_Institution

Unitive Electron. Inc., Research Triangle Park, NC, USA

fYear

1999

fDate

14-17 Mar 1999

Firstpage

218

Lastpage

220

Abstract

Chip scale packaging offers an attempt to bridge the manufacturing gulf between what has been done in the past with perimeter leaded wire-bonded packaging and what is and will be done in the future with area array flip chip packaging. In particular, chip scale packaging attempts to produce a package that can be assembled in a manner that is close to conventional. In so doing, it provides an interface to test that is comfortable and familiar. CSPs offer interconnection densities higher than conventional wire-bonding but with reduced space utilization. However, there are still choices to be made within the chip scale family and this discussion indicates an important choice in terms of assembly

Keywords

assembling; chip scale packaging; flip-chip devices; integrated circuit interconnections; soldering; CSP; CSP interconnection density; area array flip chip packaging; assembly; chip scale packaging; manufacturing; package assembly; perimeter leaded wire-bonded packaging; space utilization; wire-bonding; Assembly; Chip scale packaging; Costs; Electronics packaging; Flip chip; Lead; Manufacturing; Microprocessors; Protection; Surface-mount technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Packaging Materials: Processes, Properties and Interfaces, 1999. Proceedings. International Symposium on

Conference_Location

Braselton, GA

Print_ISBN

0-930815-56-4

Type

conf

DOI

10.1109/ISAPM.1999.757315

Filename

757315