Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture

Author

Ley, Adam W.

Author_Institution

ASSET InterTech Inc., Richardson, TX, USA

fYear

2009

fDate

1-6 Nov. 2009

Firstpage

1

Lastpage

10

Abstract

IEEE Std 1149.7 offers a means to reduce chip pins dedicated to test (and debug) access while enhancing the functionality of the Test Access Port (TAP) as a complementary superset of the original IEEE Std 1149.1 (JTAG). Extended features such as hot-plug immunity, power management, optimization of scan throughput, access to instrumentation, and access to custom technologies provide welcome improvements for debug. Further, the boundary-scan architecture is bolstered to ensure full support for test. This important advancement in test and debug interfaces is well suited for access to multiple cores on SOC or multiple die in SIP or POP.

Keywords

IEEE standards; boundary scan testing; integrated circuit testing; IEEE 1149.7 embedded tutorial; POP; SIP; SOC; boundary-scan architecture; enhanced-functionality test access port; hot-plug immunity; multiple cores; multiple die; power management; reduced-pin test access port; scan throughput optimization; Assembly; Energy management; Instruments; Packaging; Pins; Technology management; Testing; Throughput; Tutorial; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2009. ITC 2009. International

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-4868-5

Electronic_ISBN

978-1-4244-4867-8

Type

conf

DOI

10.1109/TEST.2009.5355572

Filename

5355572