DocumentCode
2702489
Title
Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra
Author
Josephs, M.B. ; Lucassen, P.G. ; Udding, J.T. ; Verhoeff, T.
Author_Institution
Centre for Concurrent Syst., South Bank Univ., London, UK
fYear
1994
fDate
3-5 Nov 1994
Firstpage
206
Lastpage
215
Abstract
Two recent developments in asynchronous circuit design are explored by means of a case study (polynomial division) in digital signal processing. The first development is a new formal method, the handshake algebra of M.B. Josephs, J.T. Udding and J.T. Yantchev (1993), that is suitable for specifying, deriving, and verifying circuits that follow a handshaking protocol. The second development is an architecture, counterflow pipelines, that R.F. Sproull (1994) has recently suggested, which is attractive to implement asynchronously
Keywords
asynchronous circuits; asynchronous DSP counterflow pipeline; asynchronous circuit design; counterflow pipelines; digital signal processing; formal design; handshake algebra; handshaking protocol; Algebra; Asynchronous circuits; Computer aided software engineering; Digital signal processing; Logic; Pipelines; Protocols; Signal design; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on
Conference_Location
Salt Lake City, UT
Print_ISBN
0-8186-6210-7
Type
conf
DOI
10.1109/ASYNC.1994.656313
Filename
656313
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