Invited address

Summary form only given. Compute performance increased by orders of magnitude in the last few decades, made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize novel architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill continues to fulfill the performance demand; however, it\´s the same Physics that helped you in the past will now pose some barriers-"business as usual" is not an option. Billions of transistors of integration capacity will be available to enable novel designs. These complex chips will have to be designed with emphasis on the system design, optimized at the system level, and with new design methodologies rather than today\´s custom or application-specific chip design methodologies. Testing should not be an after-thought. Design for test and manufacturing methodology will not be sufficient, and test hardware will have to become part of the design itself. Abundance of transistors, but with gradual faults like variations, intermittent faults like soft-errors, and slowly varying faults caused by aging demands system resiliency. Testing such complex systems with the aid of resiliency opens doors to entirely new paradigms, and testing have entirely new meaning. This paper discusses challenges and potential solutions in all disciplines, such as architecture, system design, circuits and layout, resiliency, and testing to realize these novel systems.