A new interconnection delay model considering the effects of short-channel logic gates

Author

Wu, Chung-Yu ; Shiau, Ming-Chuen

Author_Institution

Nat. Chiao Tung Univ., Hsin-Chu, Taiwan

fYear

1988

fDate

7-9 Jun 1988

Firstpage

2847

Abstract

A modeling approach to calculate the rise, fall, and delay times for short-channel CMOS inverters with interconnection lines is presented. Extensive comparisons between model calculations and SPICE simulations have shown that the analytic model has a maximum error of 16% on the delay times for CMOS inverters with interconnections of different gate sizes, device parameters, and even input excitation waveforms. Reasonable accuracy, wide applicable range, and high computation efficiency make the developed timing models quite attractive in MOS VLSI timing verification and automatic sizing

Keywords

CMOS integrated circuits; VLSI; delays; equivalent circuits; integrated logic circuits; logic design; logic gates; semiconductor device models; CMOS inverters; MOS VLSI timing verification; SPICE simulations; analytic model; automatic sizing; delay times; fall time; high computation efficiency; interconnection delay model; rise time; short-channel logic gates; timing models; CMOS logic circuits; Delay effects; Integrated circuit interconnections; Inverters; Logic gates; MOSFETs; Propagation delay; Semiconductor device modeling; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo

Type

conf

DOI

10.1109/ISCAS.1988.15532

Filename

15532