• DocumentCode
    2702884
  • Title

    Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs

  • Author

    Nagayama, Shinobu ; Sasao, Tsutomu ; Butler, Jon T.

  • Author_Institution
    Dept. of Comput. & Network Eng., Hiroshima City Univ., Hiroshima, Japan
  • fYear
    2010
  • fDate
    26-28 May 2010
  • Firstpage
    223
  • Lastpage
    228
  • Abstract
    This paper proposes a new architecture for memory-based floating-point numeric function generators (NFGs). The design method uses piecewise-split edge-valued multi-valued decision diagrams (EVMDDs). To design NFGs with less memory size, we partition the domain of the floating-point function into segments, and represent the function using an EVMDD for each segment. By realizing each EVMDD with hardware, we obtain the floating-point NFG. This paper also presents an algorithm that partitions the domain by decomposing the edge-valued binary decision diagram(EVBDD) representing the whole floating-point function. Experimental results show that, for a single-precision floating-point function, our new NFG requires 40% to 65% less memory than any previous one. An advantage of our algorithm is that it can be applied to many different functions.
  • Keywords
    Boolean functions; Computer architecture; Data structures; Design methodology; Hardware; Memory architecture; Partitioning algorithms; Signal generators; Signal processing algorithms; Table lookup; Memory-based floating-point numeric function generators; piecewise-split EVMDDs;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic (ISMVL), 2010 40th IEEE International Symposium on
  • Conference_Location
    Barcelona, Spain
  • ISSN
    0195-623X
  • Print_ISBN
    978-1-4244-6752-5
  • Type

    conf

  • DOI
    10.1109/ISMVL.2010.49
  • Filename
    5489135