DocumentCode :
2703167
Title :
PASTA: partial scan to enhance test compaction
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
1999
fDate :
4-6 Mar 1999
Firstpage :
4
Lastpage :
7
Abstract :
We propose a procedure to select flip-flops for partial scan targeting the reduction of test length. We show that significant reductions in test length can be achieved by this procedure. In addition, experimental results show that using heuristics that target the test length does not have to increase the numbers of flip-flops that need to be scanned in order to achieve a given level of fault coverage. Consequently, it may be possible to perform partial scan selection targeting the two parameters, test length and fault coverage, without requiring more flip-flops than required for one of the parameters
Keywords :
automatic testing; flip-flops; integrated circuit testing; logic testing; performance evaluation; PASTA; flip-flops; heuristics; partial scan; partial scan targeting; test compaction; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Compaction; Electrical fault detection; Fault detection; Flip-flops; Performance evaluation; Random sequences;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
ISSN :
1066-1395
Print_ISBN :
0-7695-0104-4
Type :
conf
DOI :
10.1109/GLSV.1999.757364
Filename :
757364
Link To Document :
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